This invention relates generally to semiconductor memory devices and, more specifically, to dynamic random access memory systems having both volatile and non-volatile binary data storage capability.
Semiconductor memories generally fall into three categories: serial access memories (SAMs), read only memories (ROMs), and random access memories (RAMs).
Semiconductor SAM memories are classified as charge-coupled device memories (CCDM) or bubble domain memories (BDM). CCDM and BDM systems typically involve single or multiple serial data loops with access to data stored at any particular location typically requiring serial shifting of each bit of data to a location where it can be accessed for reading or writing. The relatively long time required for accessing data precludes the use of SAMs in systems, such as RAMs, which require very rapid changing of some or all of the stored bit pattern. SAM systems are typically employed where large amounts of data need be stored but very rapid access to any particular data bit is not required.
ROMs are so designated because they are employed usually where a fixed bit pattern is required, such as for a firmware or microcode program in a data processing system. However, within the general ROM category, there exists programmable read only memories (PROMs), eraseable PROMs (EPROMs), and electrically-alterable read-only memories (EAROMs) which are sometimes designated electrically eraseable PROMs (EEPROMs). PROMs can be written one at a time only to a selected bit pattern which is permanent. EPROMs can be electrically programmed to a preselected bit pattern but typically require that ultraviolet light be shined on the device to erase the stored bit pattern. This usually requires the EPROM device to be removed from the circuit in which it is used. EEPROMS can be electrically erased and reprogrammed in the circuit environment in which they are being used. While both EPROMs and EEPROMs have the capability of altering the bit pattern stored therein, the time required for erasing and reprogramming precludes their use as random-access memory devices in memory systems which require very rapid changing of some or all of the stored bit pattern.
Semiconductor RAM systems generally fall into two categories: static RAM systems and dynamic RAM systems. Static RAM systems typically employ bistable multivibrator or flip-flop circuits in which the stored bit value is determined by the two bistable states available to the circuit. Since static RAMs employ bistable devices, the bit content of each cell is retained without refreshing and the readout of the bit content is nondestructive. In contrast, dynamic RAMs typically employ a cell arrangement in which the stored bit value is determined by the presence or absence of a voltage stored on a semiconductor capacitor structure. Dynamic RAMs typically require periodic refreshing of the information stored on the capacitor, although the readout may be either destructive or non-destructive depending upon the cell design. As a general rule, static RAM systems are favored for smaller memory systems, whereas dynamic RAMs provide lower cost per bit for, and are thus favored for larger memory systems of perhaps 32 kilobits or larger.
All version of ROMs, including EPROMs and EEPROMs, are inherently nonvolatile, that is, do not lose the bit content of the memory if electric power to the ROM is removed or lost. This inherent nonvolatility is due either to the ROM cell design or to the electrical characteristics of the devices employed in each ROM cell. RAMs on the other hand, are generally volatile devices, i.e., the bit content of the memory is lost if electric power is removed or lost.
Referring to FIGS. 1 and 2, there are shown cross-sections of conventional MOS dynamic, volatile RAM cells 10 and 20. RAM cell 20 is similar to and operates identically to cell 10, but has a two-level polysilicon gate 24 instead of the single level gate 14 of cell 10. The dual level gate 24 eliminates the diffusion 9 required in cell 10 and therefore permits size reduction and a corresponding increase in density in cell 20. During the operation of either cell, the voltage V.sub.n+ applied to the bit line diffusion 8 controls the availability of charge. Capacitors 12 (FIG. 1) and 22 (FIG. 2) are written to a "0" or "1" (charged or uncharged) state by driving V.sub.n high to enable charge transfer gates 13 and 23 to transfer any charge from diffusion 8 to the capacitor. During a read operation, the transfer gates are again turned on to transfer the charge from the capacitor to a sense amplifier (not shown) connected to the diffusion line 8.
As mentioned, RAM cells 10 and 20 are dynamic and volatile, that is, they require periodic refreshing of the information stored on the capacitors 12 and 22, and lose the stored information if electric power is removed or lost. Over the last decade or so, various approaches have been taken to add backup nonvolatile storage capability to dynamic RAMs. In general, the nonvolatile backup data storage capability can be provided by adding nonvolatile alterable threshold capacitor or transistor devices to the RAM cell. These cells will be referred to as volatile/nonvolatile dynamic RAM cells or simply V/NV RAM cells.
Exemplary V/NV dynamic RAM cells are disclosed in U.S. Pat. No. 3,771,148 to Aneshansley, U.S. Pat. No. 3,761,901 to Aneshansley and U.S. Pat. No. 3,774,177 to Schaffer, all of which are assigned to Applicant's assignee. Aneshansley '148 discloses a V/NV cell comprising a volatile capacitor and an NV transistor. The capacitor is accessed via the transistor, which is also used for NV storage during power down conditions. The Aneshansley '901 and Schaffer '177 patents disclose three-gate cells which store information in a nonvolatile gate during power-off conditions and also use the NV gate during normal volatile operation. Also, U.S. Pat. No. 4,175,291 to Spence, assigned to Applicant's assignee, discloses a four gate V/NV dynamic RAM cell which comprises a volatile storage capacitor, an adjacent, alterable threshold, non-volatile storage capacitor, and two charge transfer gates which are located one each on opposite sides of the capacitors. One transfer gate and the volatile capacitor are activated for volatile operation; both capacitors are used to effect charge transfer for V/NV store; and both transfer gates and both capacitors are used to effect NV/V restore, also by charge transfer.
Charge pumping has been applied to RAM cells, as discussed below, to enhance operation but, to Applicant's knowledge, not to V/NV RAM cells.
FIGS. 9 and 10 of U.S. Pat. No. 3,911,464 issued Oct. 7, 1975 to Chang et al., disclose an NV RAM cell which comprises a bit line diffusion and an adjacent split gate capacitor. The split gate capacitor comprises both alterable threshold and fixed threshold sections or capacitors. The alterable threshold capacitor is interposed between the bit line diffusion and the alterable threshold capacitor. The fixed threshold capacitor may be MOS (FIG. 9) or MNOS (FIG. 10).
The cell uses a charge-pumped read operation. As mentioned, the split gate capacitor comprises a fixed threshold capacitor which is interposed between the alterable threshold capacitor and the bit line diffusion. The binary state of the split gate capacitor is read by applying an alternating charge-pumping voltage to the capacitor gate to remove charge from the diffusion. For the exemplary n-channel device, charge is removed to the alterable threshold capacitor during the positive-going portion of the charge-pumping cycle, and dissipated from the alterable threshold capacitor into the substrate during the negative-going portion. The fixed threshold capacitor provides a potential barrier which blocks the alterable threshold capacitor from the bit line during the negative-going excursion of the charge-pumping voltage cycle and thereby prevents the return of charge to the bit line.
The cells treated in the '464 patent appear to be of advantageously small size. However, the cell structure and operation are entirely non-volatile, with the attendant well-known disadvantages. For example, the operating speed of such non-volatile devices is relatively slow, and, repeated writing and erasing of the non-volatile capacitor during normal operation tends to degrade the window between the binary threshold states.
The so-called NOVCID cell of the Chang et al. '464 patent is also used in the static NVRAM cell which is the subject of U.S. Pat. No. 4,091,460 to Schuermeyer et al. As is typical of static RAM cells, the Schuermeyer et al. '460 cell has two (hereafter left and right) inverter sections each of which comprises a reference node between a load device and a switching transistor. The switching transistor of each section is cross-coupled to the node of the opposite direction.
The Schuermeyer et al. '460 cell uses NOVCID loads and features V/NV charge transfer store and NV/V charge-pumped restore. The V/NV store and NV/V restore operations are as follows. Assume at the commencement of store that the cell is in a 0 state in which the right and left side nodes are high and low respectively, with the right and left side switching transistors off and on, respectively. During V/NV store, a large write voltage is applied to the gate of both lead transistors. Charge transfer from the conducting left side switching transistor writes the associated left side load to a high threshold state, while the right side load remains in the low threshold erased state. To effect an NV/V restore, an alternating charge pump signal is applied to the load gates. The charge-pumping current of the low threshold right side load exceeds that of the high threshold left side load, causing the associated right side node to reach the turn-on voltage of its coupled left side switching transistor before the left side node can turn on the right side transistor. Turn-on of the left side transistor returns the cell to the binary 0 state with the right and left side nodes, respectively, high and low.
Thus, charge pumping has been used to facilitate read/restore operations of strictly NV cells (Chang et al. '464) and static V/NV cells (Schuermeyer et al. '460). However, as mentioned, it is believed charge pumping has not been applied to dynamic V/NV RAM cells.